1. Field of the Invention
The present invention relates generally to a semiconductor device. More particularly, the present invention relates to a layout structure for a conductive layer and contact hole in a semiconductor device.
2. Description of the Related Art
Integrated circuits are typically manufactured by patterning a series of laminated masking layers. Such a masking layer includes features which are related to features on other masking layers. Each layer level in the manufacture of an integrated circuit should be spatially aligned with a previous layer level. Thus, a mask pattern to be formed on a wafer in a photolithography process should be aligned with a pattern previously formed on the wafer. masking layers. Such a masking layer includes features which are related to features on other masking layers. Each layer level in the manufacture of an integrated circuit should be spatially aligned with a previous layer level. Thus, a mask pattern to be formed on a wafer in a photolithography process should be aligned with a pattern previously formed on the wafer.
Recently, the design rule of highly integrated semiconductor memory devices has been reduced from approximately 1 xcexcm, the level of mega-bit grade DRAMs, to approximately 0.15 xcexcm, the level of giga-bit grade DRAMs. The design rule is a factor associated with a process limitation. In particular, the alignment tolerance in the deep submicron design rule is an important factor for determining a fatal failure of devices. Thus, the alignment margin of a pattern formed in a pre-process or post-process with a reduced design rule has been highlighted.
In the case of a dynamic random access memory (DRAM), a reduction in memory cell pitch results in a reduction in the alignment margin between a contact hole, serving to electrically connect the source region of an associated transistor to the storage electrode of an associated capacitor, and the storage electrode formed over the contact hole. Such a reduction in the alignment margin may be a major factor causing a degradation of the device.
FIG. 1 is a plan view showing the layout of a storage electrode in a capacitor manufactured with a conventional method, and FIG. 2 is a cross-sectional view taken along the line 2xe2x80x942 in FIG. 1. An insulating material such as an oxide is deposited over a semiconductor substrate 10 previously formed with conductive elements such as transistors and bit lines, thereby forming an insulating layer 12 over the semiconductor substrate 10. The insulating layer 12 is then etched using a photo-etch process, thereby forming contact holes 14 for exposing conductive regions of the substrate 10, for example, source regions (not shown) of respective transistors.
Subsequently, a conductive layer 16 such as a doped polysilicon layer is deposited over the resulting structure to a desired thickness from the upper surface of the insulating layer 12, with a chemical vapor deposition method, such that each contact hole 14 is completely buried by the conductive layer 16. The conductive layer 16 is then etched using a photo-etch process, thereby forming respective storage electrodes of capacitors. Each storage electrode denoted by the reference numeral 16 is electrically connected to the source region of an associated one of the transistors through an associated one of the contact holes 14. As shown in FIG. 1, each storage electrode 16 has a linear layout when viewed in a plan view. Thus, storage electrodes 16 are repetitively arranged while being spaced apart from one another by a uniform distance.
In the structure according to the above described conventional method, when each storage electrode has a reduced size to obtain an increased integration degree, the alignment margin (denoted by the reference character L in FIGS. 1 and 2) between the storage electrode and the contact hole under the storage electrode may be insufficient. This is because it is difficult to reduce the size of the contact hole to a desired extent due to a process limitation involved in the photolithography process. In such a case, there is a problem in that the storage electrode may be excessively etched at the open end of the contact hole in the etch process for forming the storage electrode.
FIG. 3 is a scanning electron microscope (SEM) photograph showing an inferior electrode pattern resulting from an insufficient alignment margin between the storage electrode and the contact hole. Referring to FIG. 3, the contact hole is not completely covered by the storage electrode at the open end thereof. As a result, there may be a leakage of cell capacitance at the portion of the contact hole not covered by the storage electrode.
To solve the above-described problem, attempts to reduce the size of the contact hole to a process limit in the photolithography process or below have been made. However, such methods are problematic in that the contact hole may not be completely open.
To protect the contact hole from the etch process for forming the storage electrode, a method has been proposed in which nitride film spacers serving to prevent the contact hole from being etched are respectively formed at opposite side walls of the contact hole prior to the deposition of a conductive layer for the storage electrode. This method, however, involves a drawback in that the number of processes used increases. Furthermore, the nitride film spacers may serve as a source of diverse defects.
A feature of the present invention is to provide a layout in a semiconductor device capable of achieving an improvement in the alignment margin between a conductive layer and a contact hole under the conductive layer pattern.
The present invention provides a semiconductor device including: a conductive region and a conductive element electrically connected to the conductive region via a contact hole beneath the conductive element, the conductive element defining a first longitudinal end and a second longitudinal end opposite the first longitudinal end, the first longitudinal end defining a first width and the second longitudinal end defining a second width different from the first width. In one embodiment of the present invention, the first width is larger than a width of the contact hole and the second width is smaller than the first width. Additionally, the second width is smaller than the width of the contact hole. Further, the first width is larger than the second width and a distance between the contact hole and the first end is less than a distance between the contact hole and the second end. Further still, the conductive element defines a trapezoid.
The present invention also provides a semiconductor device including: a plurality of conductive regions and a plurality of conductive elements on a common plane, each element connected to a respective conductive region via a respective contact hole beneath the conductive element, each element defining a first longitudinal end and a second longitudinal end opposite the first longitudinal end, the first longitudinal end defining a first width and the second longitudinal end defining a second width smaller than the first width, each element oriented such that the first end is opposite the second end of an adjacent element, and the second end is opposite the first end of the adjacent element. In one embodiment, the conductive element defines a trapezoid and a distance between the contact hole and the first end is less than a distance between the contact hole and the second end.
The present invention further provides a semiconductor device including: a conductive region and a capacitor including: a first electrode electrically connected to the conductive region via a contact hole beneath the first electrode, the first electrode defining a first longitudinal end and a second longitudinal end opposite the first longitudinal end, the first longitudinal: end defining a first width and the second longitudinal end defining a second width different from the first width and a second electrode laminated over the first electrode such that a dielectric element is interposed between the first and second electrodes. In one embodiment of the present invention, the first width is larger than a width of the contact hole and the second width is smaller than the first width. Additionally, the second width is smaller than the width of the contact hole. Further, the first width is larger than the second width and a distance between the contact hole and the first end is less than a distance between the contact hole and the second width. In addition, the first electrode defines a trapezoid.
The present invention still further provides a semiconductor device including: a plurality of conductive regions; a plurality of first electrodes on a common plane, each first electrode connected to a respective conductive region via a respective contact hole beneath the first electrode, each first electrode defining a first longitudinal end and a second longitudinal end opposite the first longitudinal end, the first longitudinal end defining a first width and the second longitudinal end defining a second width smaller than the first width, each first electrode oriented such that the first end is opposite the second end of an adjacent first electrode, and the second end is opposite the first end of the adjacent first electrode; and a second electrode laminated over the first electrodes with a dielectric interposed between the first electrodes and second electrode. In one embodiment of the present invention, between the contact hole and the first end is less than a distance between the contact hole and the second end.
The present invention still further provides a layout in a semiconductor device having a conductive layer electrically connected to a conductive region via a contact hole beneath the conductive layer, wherein the conductive layer has a layout with different widths at opposite longitudinal ends thereof, respectively. In one embodiment of the present invention, the conductive has a layout configured such that the width at one of the longitudinal ends thereof is larger than the width of the contact hole, and the width at the other longitudinal end thereof is smaller than the width of the one longitudinal end. Additionally, the conductive layer has a layout configured such that the width of the other longitudinal end thereof is smaller than the width of the contact hole. Further, the conductive layer is repetitively arranged on a common plane to form an array of conductive layers such that the wider and narrower longitudinal ends of one conductive layer face respective wider and narrow longitudinal ends of another conductive layer adjacent to the one conductive layer.